ADZS-21469-EZLITE【PDF 15/62 页】KIT EVAL EZ LITE ADSP-21469

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Preliminary Technical Data

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

Table 7. Pin List (Continued)

State

During

SSTL1 and After

Name

Type

LVTTL 8

Reset Description

LDAT0 7–0

I/0

?

High-Z

Link Port Data (Link Ports 0–1) . When configured as a transmitter, the

LDAT1 7–0

port drives both the data lines.

LCLK0

I/O

?

High-Z

Link Port Clock (Link Ports 0–1). Allows asynchronous data transfers.

LCLK1

When configured as a transmitter, the port drives LCLKx lines. An

external 25k Ω pull-down resistor is required for the proper operation

of this pin.

LACK0

I/O

?

High-Z

Link Port Acknowledge (Link Port 0–1). Provides handshaking. When

LACK1

the link ports are configured as a receiver, the port drives the LACKx line.

An external 25k Ω pull-down resistor is required for the proper

operation of this pin.

THD_P

THD_M

I

O

Thermal Diode Anode

Thermal Diode Cathode

TDI

I (pu)

?

Test Data Input (JTAG). Provides serial data for the boundary scan

logic. TDI has a fixed internal pull-up resistor.

TDO

O /T

?

High-Z

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS

I (pu)

?

Test Mode Select (JTAG). Used to control the test state machine. TMS

has a fixed internal pull-up resistor.

TCK

I (pu)

?

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must

be asserted (pulsed low) after power-up or held low for proper

operation of the device.

TRST

I (pu) 1, 2

?

Test Reset (JTAG). Resets the test state machine. TRST must be asserted

(pulsed low) after power-up or held low for proper operation of the

processor. TRST has a fixed internal pull-up resistor.

EMU

O/T (pu) 1, 2

?

High-Z

Emulation Status. Must be connected to the ADSP-2146x Analog

Devices DSP Tools product line of JTAG emulators target board

connector only. EMU has a fixed internal pull-up resistor.

CLK_CFG 1–0

I

?

Core to CLKIN Ratio Control. These pins set the start up clock

frequency. See Table 10 for a description of the clock configuration

modes.

Note that the operating frequency can be changed by programming

the PLL multiplier and divider in the PMCTL register at any time after

the core comes out of reset.

BOOT_CFG 2–0

I

?

Boot Configuration Select. These pins select the boot mode for the

processor. The BOOTCFG pins must be valid before reset is asserted. See

Table 9 for a description of the boot modes.

RESET

I (pu)

?

Processor Reset. Resets the processor to a known state. Upon

deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After

this time, the core begins program execution from the hardware reset

vector address. The RESET input must be asserted (low) at power-up.

XTAL

O

?

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive

an external crystal.

Rev. PrC

| Page 15 of 62 | January 2009

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